Timing Convergence Lead (STA)

Job Details:

Job Description:

Shape the Future of Data Centers and Do Something Wonderful! 

Intel put the Silicon in Silicon Valley. No one else is obsessed with engineering a brighter future. Every day, we create world-changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. 

Who We Are 

Intel is revolutionizing the Data Center and Server segment. Join us and change the way the world builds servers. Intel's Data Center group is seeking talented and enthusiastic designers to join our growing team and take part in developing state-of-the-art servers that will move data at higher speeds in the Data Center, enriching the lives of every person on Earth. 

Your Mission as Timing Convergence Lead 

As our Timing Convergence Lead, you'll be at the forefront of cutting-edge semiconductor design, ensuring our next-generation server processors meet the most demanding performance requirements. You'll drive timing closure across complex, multi-domain designs that power the world's data infrastructure. 

Key Responsibilities: 

• Lead STA Excellence: Drive setup, convergence, reviews, and sign-off for multi-mode, multi-corner, multi-voltage domain designs 
• Master Timing Closure: Perform comprehensive timing analysis and closure at Partition/Sub-system/FC levels 
• Influence & Collaborate: Drive convergence by partnering with APR and Design teams as a key stakeholder 
• Innovate Methodologies: Develop constraint strategies and provide expert feedback on Clock Tree Synthesis (CTS) approaches 
• Pioneer ECO Solutions: Lead timing ECO implementation strategy development and enable Tweaker/Prime Time ECO flows 
• Automate & Optimize: Create automation scripts within STA tools for methodology advancement 
• Solve Complex Challenges: Apply excellent debugging skills to implementation issues with creative, breakthrough solutions 
• Evaluate & Advance: Assess multiple timing methodologies and tools across various designs and technology nodes 

Technical Expertise: 

• Deep expertise in digital design implementation (RTL to GDSII) using Synopsys/Cadence tools 
• Strong understanding of LVF/POCV variation formats and deep sub-micron design challenges 
• Proven experience with constraint development and cleanup 
• Knowledge of advanced CTS strategies and timing optimization techniques 

Qualifications:

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications 

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM-related field 

• 4+ years of experience in Static Timing Anaysis (STA)
• Experience in one or more of the following: OCV/POCV/LVF, MMMC, Clock Tree Analysis, and SI/Noise analysis. 
• 4+ years of experience with industry-standard STA tools:  • Synopsys PrimeTime (preferred) or Cadence Tempus. 
• Experience enabling Tweaker/PrimeTime based ECO flows and closure methodologies on complex multi-voltage designs 

• Scripting experience i.e. Tcl, Python, or Perl for automation. 
• Experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm) 

Preferred Qualifications 

• Post graduate degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM-related field 
• Server design experience - a significant plus! 

Why Choose Intel? 

• Join a team that's not just building processors – we're engineering the future of computing. Your work will directly impact how data centers worldwide operate, making them faster, more efficient, and more powerful. At Intel, your innovations don't just advance technology; they enrich lives globally. 

Ready to do something wonderful? Apply now and help us build tomorrow's data infrastructure today! 

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

US, Oregon, Hillsboro, US, Texas, Austin

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.