Technologist, ASIC Development Engineering (PD Methodology & CAD Flow Architect/Lead)

SanDisk is uniquely positioned at the heart of the AI-driven data economy, with a focused portfolio centered on advanced NAND flash and SSD technologies that underpin cloud, enterprise, and hyperscale infrastructures. As AI workloads continue to explode in scale and complexity, the need for high-throughput, low-latency, and energy-efficient storage has become mission-critical—an area where SanDisk’s technology leadership clearly stands out.

Now operating as a focused, independent storage company, SanDisk has sharpened its execution and innovation engine to serve the rapidly growing AI, data center, and edge markets. Its inclusion in the S&P 500 is a strong validation of both its operational maturity and its relevance as a core infrastructure player in the global technology ecosystem.

 As AI increasingly moves from training to large-scale inferencing, storage plays a decisive role in system performance. Fast access to models, embeddings, and real-time data requires ultra-low latency, high endurance, and power-efficient storage—particularly in distributed and edge deployments. SanDisk’s flash-based solutions are well aligned to enable efficient, scalable AI inferencing by minimizing data movement bottlenecks between compute and storage.

Driven by experienced leadership and a clear long-term vision, SanDisk is not just responding to the AI wave—it is helping define the storage foundation on which next-generation AI systems will be built.

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-class NAND Flash products used globally at massive scale. Design Enablement team enables the Technology, Methodology and Flows to the Physical Design team to deliver best in class products. As the PD Methodology / CAD Lead, you will play a pivotal role in defining, architecting, and delivering robust RTL-to-GDS physical design methodologies on cutting-edge technology nodes, enabling best-in-class PPA, quality, and productivity.

This role is ideal for a seasoned PD methodology leader who enjoys solving complex cross-domain problems, working closely with foundries, and driving innovation across flows, tools, and teams.

Key Responsibilities

• Lead and mentor the PD Methodology/CAD team to deliver scalable, production-ready flows and innovative solutions across multiple programs.

• Design and architect end-to-end PD methodologies (RTL to GDS) for advanced technology nodes, ensuring correctness, robustness, and scalability.

• Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices.

• Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions.

• Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence.

• Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules.

• Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability.

• Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity.

• Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges.

• 10+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs.

• Deep, hands-on understanding of complete PD flow, including:

• Synthesis

• Logical Equivalence Checking (LEC)

• DFT insertion and integration

• Place & Route

• Static Timing Analysis (STA)

• Physical Verification

• EM/IR analysis

• Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA.

• Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes.

• M.Tech in VLSI Design or a related field (or equivalent industry experience).

• Proficiency in scripting and automation using TCL, Perl, and/or Python.

• Experience working in multi-project, high-complexity environments with tight schedules.

 

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Desirable Skills

• Exposure to advanced nodes  and complex signoff requirements.

• Experience with memory controllers or high-performance data-path designs.

• Prior experience applying AI/ML in EDA or design automation is a strong plus.

• Strong communication and stakeholder management skills.