Standard Cell Design Reliability Verification Engineer

Job Details:

Job Description:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a Master's degree with 5+ years of relevant industry experience or PhD degree with 1+ years of relevant industry experience in the field of Electronics, Electrical and/or Computer Engineering or related fields with specialization in VLSI and knowledge in:
- Extensive experience in all aspects of the IR and EM flows for Standard cells at device level and ASIC designs.
- In depth understanding of EM and IR flows methodologies using Synopsys Primelib RV, PrimesimEMIR, PrimesimXA RV, Ansys RHSC and Cadence Voltus tools with associated Process Design Kit collaterals dependency.
- Expertise with Reliability verification in lower nm nodes and EM/IR concepts with a proven track record in establishing RV flows, debug problems and drive solutions working with cross functional teams and EDA vendors.
- Digital circuit design, including CMOS combinatorial logic and sequential element design and layout.
- Strong understanding of device physics, FinFet characteristics and Standard Cell Library design.
- Strong Python programming and automation skills.
- Excellent understanding of various Standard Cell Library collaterals and PV Timing Analysis.
- Good understanding of a) Development of automation for library modeling, validation, quality checking, performance, and reliability verification b) Standard library release build, validation, QA, release, and support c) Technically lead a team of engineers, debug problems, remove execution roadblocks, detailed planning of execution/releases, and work on strategic initiatives for future technologies d) Parasitic extraction and circuit optimization for power/performance/robustness/density.
- Excellent collaboration skills across geographically distributed teams and being able to handle ambiguity while developing expertise in new areas and delivering excellent, quantifiable results will be key to the success in this role. The successful candidate must possess excellent written and verbal communication skills, strong customer/result orientation and the ability to work with external, internal partners and with EDA vendors in a flexible manner.

Preferred Qualifications:
Experience with Industry standard tools - Synopsys Primelib RV, PrimesimEMIR, PrimesimXA RV, Ansys RHSC, Cadence Voltus, Design Compiler, Genus, Tempus, ICV Experience in digital circuit design, front end model creation and functional verification. Experience with standard cell library characterization, thermal models, emt models, liberty models and cross validations with front end models and liberty models. Industry Experience on Reliability verification of standard cells covering ERC, EM, SH, FinFet self-heating. Experience working with EDA vendors to drive new features and capabilities. Knowledge of industry-standard EDA tools for VLSI circuit and layout design. Experience working in the Linux environment and its development tools. Standard cell level PPA modeling, simulation, and ROI analysis. Experience in CMOS power modeling and cell level optimization. CMOS and standard cell level device variation and Aging analysis. Engineering acumen and analytical skills. Debugging skills. Customer oriented and able to work in a dynamic environment.
Requirements listed would be obtained through a combination of industry relevant job experience, and or schoolwork/classes/research

Qualifications:

Design Technology Platform (DTP) organization, collaborating closely with partners in process technology, IP, and products spanning client/server and networking products. The primary focus of AD-FIP is to guide process technology definition, design prototypes in Intel's latest process technology, develop Foundational IP's supporting Intel's internal and external design customers. In this position, you will participate in the design, development, benchmarking, validation of standard cell libraries using leading process technologies for use in the design of Intel's next-generation SoCs and microprocessors to meet critical design specifications, including power, performance, area, and cost.
Primary responsibilities include: Lead Reliability verification and capabilities for standard cells covering EM, SH, FinFet self-heating; layout compliance for reliability conditions. Drive engagement with internal partners and external EDA vendors to coordinate tool feature requirements and specification, definition for reliability verification. Build and release EMT, Thermal and Plimit (Power-switch) collaterals for Standard cell library for internal and external customers for Intel's newest process technologies after validation sign-off.
Other areas of exposure and involvement will include one or more of the areas mentioned below: Digital logic, standard cells design, development, benchmarking in advanced nodes, debug problems. Design and implementation of the combinatorial, clock, power management, and sequential circuits for Intel's newest process technologies. Layout development, optimization and validation. Parasitic extraction and circuit optimization for power/performance/robustness/density. Library characterization for timing, noise, power, and variation models (non-linear delay models; composite current source models, parametric on-chip variation models). Physical View (NDM, LEF, OASIS, OALIBS) generation for standard cell libraries. APL characterization and Modeling. Developing functional models behavioral Verilog, power udp Verilog and fault models. Development of automation for library Modeling, validation, quality checking, performance, and reliability verification. Block Regression, generation of PPA data and comparison against PDK expectation, previous library revisions, root cause differences and report for library user's consumption. Library build, validation, QA, release, and support.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.