VLSI Verification Engineer

EROSTechnologiesInc

Santa Clara, CA, United States contract

Posted: August 10, 2016

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Quick Summary

Verification engineers – OVM/UVM are responsible for verifying the functionality of digital circuits and systems, ensuring they meet the required specifications and standards.

Required Skills

Verification Subsystems DDR Modem

Job Description

EROS Technologies was founded with a simple motive of offering the clients exactly what they want, how they want and when they want it. By leveraging for its clients its technological edge and right-sourcing advantage, EROS in a short period of time has grown to become one of the most trusted strategic technology partners. Treating every client as the top priority, we customize our solutions and services to align with the unique needs of each client.

Job Title: VLSI Verification Engineer

Location: Santa Clara, CA

Duration 6 Month Contract

Job description:

Verification engineers – OVM/UVM is Mandatory
CPU subsystem/DDR/Modem verification

All your information will be kept confidential according to EEO guidelines.

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