Verifikationsingenieur – UVM / SystemVerilog

Confidential

München, Germany Freelance

Posted: December 9, 2025

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Required Skills

SystemVerilog UVM Cadence Synopsys Mentor EDA SVA Python Perl Tcl

Job Description

Beschreibung:
Verantwortlich für die funktionale Verifikation von digitalen IC-/ASIC-/SoC-Designs. Aufbau von Testbenches, Entwicklung von UVM-Komponenten und Sicherstellung einer vollständigen Coverage.

Typische Aufgaben:
Entwicklung von UVM-Testumgebungen
Erstellung und Ausführung von Testfälle...

Source: freelancermap — View full description on freelancermap →

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