Verifikationsingenieur – UVM / SystemVerilog

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München Remote

Posted: November 25, 2025

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Required Skills

SystemVerilog UVM Cadence tools Synopsys Mentoring EDA tools SVA Python Perl TCL

Job Description

Projektbeschreibung
Beschreibung:
Verantwortlich für die funktionale Verifikation von digitalen IC-/ASIC-/SoC-Designs. Aufbau von Testbenches, Entwicklung von UVM-Komponenten und Sicherstellung einer vollständigen Coverage.

Typische Aufgaben:

Entwicklung von UVM-Testumgebungen

Erstellung und Ausf...

Source: freelance.de — View full description on freelance.de →

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