Tech Lead Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Tech Lead VLSI Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Tech Lead VLSI Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

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Design Ownership & Implementation

• Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support

• Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions

• Serve as the point of contact for your logic blocks, driving technical decisions and quality

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Quality Assurance & Design Optimization

• Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient

• Apply advanced design techniques to meet aggressive PPA (Power, Performance, Area) targets

• Drive design quality through comprehensive verification and validation activities

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Cross-Functional Collaboration & Methodology Innovation

• Interact closely with Architecture, Verification, and Backend teams to ensure seamless integration

• Participate in design methodology improvements and tool automation initiatives

• Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field

• 7+ years of experience in logic design at semiconductor companies

• Strong knowledge and experience in Verilog and/or SystemVerilog

• Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis

• Excellent communication skills with ability to work effectively across teams

• Experience working on complex digital designs from specification to implementation

Preferred Qualifications

• Master's degree in Electrical Engineering or related field

• Knowledge of DDR and PCIe protocols and implementation

• Understanding of power management techniques for low-power design

• Proficiency in scripting languages such as Python or Perl

• Experience with high-speed serial interface designs or connectivity protocols

• Background in advanced process technologies (7nm and below)

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.