Team Lead Digital Verification

Who are we?
Imagine being part of the dynamic journey at Qualinx – a startup born when three visionary PhD Engineers from TU Delft set out to revolutionize radio chip technology. At Qualinx, we're on a mission to conquer the high-power consumption challenges in Global Navigation Satellite Systems and IoT sensors. With a great team of over 40 individuals, scaling to 60 next year, hosting more than 18 nationalities, we've achieved the impossible - the world's lowest power GNSS chipset. Now, we're on the verge of unleashing our game-changing digital RF technology product, ready to flood the market with millions of annual shipments.

What Sets Us Apart

Joining Qualinx isn't just about a job; it's about embracing high standards, and boldly navigating unexpected challenges. We thrive on collaboration, with a commitment to self-improvement and product excellence. At Qualinx, you're not just an employee; you're an integral part of our exciting journey, contributing to the growth and success of a ground breaking solution.

Job Description

As a Team Lead Digital ASIC Verification Engineer, you'll play a role in shaping the future of our cutting-edge technology. You will be responsible for the verification of our digital IP blocks and the simulation of Chip level post-layout within our upcoming SoCs. You will contribute to the circuit design for our next-generation products.

• You are responsible for ASIC verification, System Verilog, and UVM.

• You will be responsible for the simulation and verification of digital block implementation in RTL for various functions, including control state machine digital processing (DSP), and multiple clock domain interface management.

• During your work at Qualinx you will be responsible for the post-layout simulation of complex mixed-signal SoC.

• As a Digital ASIC Verification engineer you will develop test benches and test cases for block-level functional verification.

• You will work with our backend and implementation teams to address synthesis, timing, DFT issues for the ASIC implementation.

• You understand all design integration activities like Lint, CDC, Synthesis & ECO.

• You will define the verification and test plan, run regressions, reproduce, and debug functional and performance bugs.

• You are responsible for the verification of various IPs/Sub IPs integrated to the top level SoC.

• Lastly: you will have an understanding of the design synthesis and fix timing issues for the Physical Design team.