Sr Staff CPU Core/Unit Verification Engineer, Functional Safety

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are seeking a passionate and detail-oriented Design Verification Engineer to join our Functional Safety (FuSa) IP team. You will work on verifying safety-critical IPs designed to meet ISO 26262/ASIL-B/ASIL-D and similar safety standards, ensuring correctness, robustness, and resilience. The ideal candidate will bring strong verification fundamentals and an interest (or experience) in safety verification.We welcome candidates at various experience levels for this role.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced DV engineer with SystemVerilog, C++ and UVM expertise.

• Strong interest in safety-critical design and understanding of ISO 26262 ISO (ASIL
levels B–D). or other safety standards.

• Able to work independently and deliver in a highly accountable environment.

• Team player who communicates clearly and thrives in cross-functional teams.

What We Need

• Ability to build C++/UVM environments and author safety-focused test plans.

• Experience with fault injection, resilience testing, or safety diagnostics.

• Hands-on experience with Synopsys VC Z01X, Siemens Tessent or Cadence Safety
Verification for fault simulation and analysis.

• Work closely with safety architects and designers to validate safety mechanisms and
Analyze fault simulation results to measure and report diagnostic coverage (SPFM, LFM,
PMHF).

• Ensure traceability of safety requirements from PRD → RTL → testbench → Stimulus →
results.

What You Will Learn

• Practical verification for IPs with ASIL-level safety requirements.

• Functional Safety methodologies and compliance tracking in real projects.

• Integration of safety IPs into CPU and system architectures.

• Development of cutting-edge safety features in next-gen compute platforms.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.