Senior SoC Design Engineer

About Celestial AI

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

ABOUT THE ROLE

We are seeking a Senior SoC Design Engineer to contribute to the design, integration, and implementation of complex System-on-Chips (SoCs). This role involves hands-on work with high-speed interconnects, IP integration, and the full ASIC implementation flow. You will own the micro-architecture, RTL design, and synthesis, working closely with verification and the physical design team.

We want to hear from you if you have strong experience in SoC integration, high-speed interfaces, or ASIC implementation.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• SoC Design & IP Integration:

• Integrate and configure high-speed IPs (e.g., UCIe, CXL, PCIe, Serdes) into SoC designs.

• Define and integrate AXI-based Network-on-Chip (NoC) interconnects and subsystems.

• Collaborate effectively with cross-functional teams, including IP vendors, verification, and physical design, to ensure seamless integration and debug.

• ASIC Implementation & Sign-off:

• Create the micro-architecture, RTL design, synthesis, and be responsible for design quality (Lint, CDC, and RDC).

• Optimize RTL for power, performance, and area (PPA) goals.

• Verification & Debug:

• Work with pre-silicon verification teams to ensure design is verified.

• Provide inputs for the test plan covering functionality, corner cases, functional coverage

• Run tests and debug, work with the verification team to close coverage, resolve design, timing, and protocol compliance issues in close collaboration with verification and firmware teams.

• Participate in post-silicon bring-up and debug efforts.

• Support emulation and FPGA-based prototyping for early IP validation.

QUALIFICATIONS

• Education & Experience:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

• 5+ years of hands-on experience in ASIC/SoC design, integration, and implementation.

• Technical Expertise:

• SoC Design & RTL:

• Strong experience in RTL design and integration using Verilog/SystemVerilog.

• Experience working with interconnect protocols like AXI.

• Experience integrating high-speed interfaces (e.g., UCIe, CXL, PCIe, DDR).

• ASIC Implementation:

• Hands-on experience with logic synthesis, static timing analysis (STA), and low-power design techniques.

• Proficiency with common EDA tools for synthesis and STA.

• Knowledge of physical design constraints, floorplanning, and the timing closure flow.

• Verification & Debug:

• Familiarity with pre-silicon verification methodologies (e.g., UVM).

• Strong problem-solving skills with a methodical approach to debugging.

• Familiarity with post-silicon bring-up and debug techniques is a plus.

• Scripting:

• Proficiency in scripting languages like Tcl or Python for automation and debug.

PREFERRED QUALIFICATIONS

• Experience working with UCIe/CXL/PCIe/Serdes would be a plus for this role.

LOCATION: Santa Clara, CA, or Orange County, CA

For California Location:

As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000.00 - $215,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.

We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.

Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.

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