Senior RTL Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

About the Role:

We are seeking a Senior RTL Design Engineer to join our high-performance design team working on next-generation transceiver ips, 200G/400G/800G/1.6T PCS Layer and high-speed DSP implementation. In this role, you will contribute to the development of high-speed, low-power digital designs, collaborate with cross-functional teams, and ensure that your RTL code meets performance, area, and power goals for cutting-edge transceiver architectures.

Key Responsibilities:

• Develop synthesizable RTL for high-speed Ethernet, UAlink, PCIE, multi-gigabit transceiver IPs in Verilog/System Verilog.

• Design and implement control and data path logic for key transceiver subsystems (e.g., 64/66b encoder, scramble, gearbox, alignment, interleave, FEC…).

• Collaborate with the architecture, verification, DFT, physical design, and firmware teams throughout the design cycle.

• Perform functional simulations and waveform analysis to verify design correctness.

• Optimize designs for power, performance, and area (PPA) in collaboration with synthesis and STA engineers.

• Writing Micro-Architecture Specification for the design.

• Support timing closure and debug logic issues in post-synthesis and post-layout simulations.

• Generate and maintain documentation (specifications, design guides, timing constraints).

• Develop automation scripts (Tcl, Python, Perl) to improve RTL development, linting, and synthesis flows.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

• 2+ years of experience in RTL design for high-performance digital designs (preferably ≤ 5nm).

• RTL coding using Verilog/SystemVerilog

• Synthesis and linting tools (e.g., Design Compiler, SpyGlass)

• Debugging functional and gate-level simulations

• Familiarity with timing constraints (SDC), CDC/Reset design, and scan insertion.

• Experience integrating IPs and working with hierarchical RTL designs.

• Hands-on experience with simulation tools (VCS, Questa, Xcelium).

Pay and Benefits:

• Competitive salary.

• Performance bonus each year.

• Flexible working time.

• Health checks each year.

• Insurance for engineer and family.

• Lunch Allowance.

• Company trips.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.