Senior Principal Physical Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

About the Role

We are seeking a Senior Principal Physical Design Engineer to lead and innovate in the physical implementation of our next-generation AI connectivity silicon. In this role, you’ll take ownership of RTL-to-GDSII flows for complex SoCs and IPs, solve the most challenging implementation problems at advanced nodes (2nm, 3nm, 5nm), and mentor engineers across the global design team.

This position offers the opportunity to make a significant technical and strategic impact on our silicon platforms as we scale to meet the demands of AI workloads in cloud and hyperscale environments.

Key Responsibilities

• Lead and drive IP/macro block-level physical implementation from RTL to GDSII, focusing on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems.

• Architect implementation strategies for AI SoCs and chiplets, supporting complex clock/power domains and hierarchical floorplans.

• Collaborate with RTL, STA, DFT, packaging, and verification teams to ensure timing and physical convergence.

• Own advanced physical design tasks including:

• EM/IR and power grid optimization for high-current blocks

• Congestion mitigation and routing-aware floorplanning

• RC-aware timing closure across corners and PVTs

• Clock tree synthesis and skew management across domains

• Lead chiplet integration efforts with emphasis on die-to-die interfaces, timing alignment, and physical abstraction.

• Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk).

• Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools.

• Act as a technical mentor, reviewing designs, guiding junior engineers, and contributing to global technical leadership.

• Interface with EDA vendors and TSMC for tool qualification and design enablement.

Required Qualifications

• Master’s or PhD in Electrical or Electronics Engineering from a leading institute.

• 10+ years of experience in physical design with multiple successful tapeouts at ≤5nm technology nodes.

• Strong hands-on expertise in floorplanning, placement, CTS, routing, timing, power analysis, and signoff.

• Proficiency with EDA tools such as Cadence Innovus, Synopsys FC, Calibre, Voltus, RedHawk.

• Demonstrated experience in implementing SerDes, PHYs, or high-bandwidth interconnects (e.g., PCIe, CXL).

• Proven ability to collaborate across domains and lead technical efforts from spec to silicon.

Preferred Qualifications

• Experience with AI/ML SoC designs, chiplet architectures, or UCIe interfaces.

• Exposure to high-speed analog/mixed-signal integration and co-design.

• Familiarity with signal/power integrity considerations for high-performance computing.

• Contributions to patents, publications, or conference presentations in the field.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.