Senior IP Logic Design Engineer.

Job Details:

Job Description:

The Data Centre-Design Silicon Engineering  delivers leadership Xeon products to cloud and datacenter customers through development of industry leading x86 core and differentiated IPs that enhances product performance and competitiveness in both Xeon, Networking & AI platforms. IP design group within DCG designs Coherent Fabric IP, Memory controller, NOC, PCIe, UCIe controllers and many fundamental building blocks for the Xeon server SOCs.

We are seeking an experienced Micro Architect/Senior Design Engineer to design, develop, and implement advanced Digital IO Controllers like PCIe/CXL/UCIe systems for next-generation data center and AI chips. This role requires a unique blend of microarchitectural expertise and hands-on RTL coding skills to bring cutting-edge designs to life. The ideal candidate will have a deep understanding of high speed IOs like PCIe/CXL/UCIe Protocol and architecture, interconnect protocols, and coherency mechanisms, coupled with a proven ability to implement these designs at the RTL level.

• Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
• Design and implement critical components of the PCIe/UCIe controller microarchitecture & RTL Blocks and with best in class KPIs  Power perf & area @ high-speed clocking.
• Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation.
• Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems.
• Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases.
• Mentor junior engineers and contribute to technical reviews and design documentation.
• Stay updated with emerging technologies and trends in PCIe/CXL/UCIe protocols, and AI/ML hardware.
• Strong problem-solving and debugging skills.
• Excellent communication and collaboration abilities.
• Ability to manage and prioritize multiple tasks effectively.

Qualifications:

Minimum Qualifications:

Bachelor of Engineering in engineering with minimum 8-12+ years of experience/Master of Engineering with 7-11+ years of relevant experience in Digital design, System Verilog, RTL Design, FE RTL2Netlist methodology flows, STA, Formal Equivalence etc.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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