Senior IC Physical Failure Analysis Engineer
NVIDIA
Posted: April 7, 2026
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Quick Summary
This role involves analyzing physical failure of IC's using dual-beam PFIB and TEM sam.
Required Skills
Job Description
NVIDIA Networking IC Product Engineering team is looking for a highly skilled IC physical failure analysis (PFA) engineer to join our growing team and support PFA activities for yield improvement, product bring-up, customer returns, and product qualification. As a PFA engineer, you will own the physical failure analysis (PFA) part, develop work procedures/techniques/recipes, and perform PFA of IC’s using in-house equipment and in external labs.
What You Will Be Doing:
Opera
• te dual-beam PFIB and develop workflows for the following applications:
• Site-specific cross-sectioning
• TEM sample preparation
• IC delayer
• Large scale cross-sections
• Unique sample preparation for different probing and imaging techniques
Use
• SEM based nanoprobing techniques for fault isolation and device/cell characterization based on FA plan provided by the EFA engineers
• EBAC/EBIC/EBRICH for fault isolation
• Device and cell level measurements
• Own and lead nanoprobing activities, including method development and execution. Continuously drive improvements, stay up-to date, and collaborate with vendors on new techniques.
• Sample preparation for optical fault isolation, probing and more: use P-lapping and CNC for Si thinning and IC delayering
What We Need to See:
• BSc in Materials/chemical engineering, physics, chemistry, or related fields
• 5+ years of relevant industry experience in IC package or die level Failure Analysis.
• Ability to work and collaborate as part of a team and independently
• Self-motivated with the ability to learn alone and review the literature to find solutions to our challenges.
• Insist on high standards for high-quality samples
• Good documentation and communication skills
Ways To Stand Out From The Crowd:
• Good understanding of VLSI circuit design, and/or device physics, and/or IC process engineering
• Experience with various IC delayering methods
• Background with dual beam FIB for cross-sections and preparing lamella for TEM
• Experience with SEM based nano-probing