Principal Engineer, Design Technology Co-optimization

Job Details:

Job Description:

Organization Description

Advanced Design & Foundational IP (ADFIP) is part of Design Technology Platform (DTP) under Foundry Technology Development. ADFIP's core focus is design-technology co-optimization (DTCO), system-design co-optimization (STCO) and foundational IP development to support Intel technology development, internal client/server/NEX products and external tie0/tie1 customers. The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mmWave circuits and 3D IC, and conducts comprehensive Si validation on process and package development test vehicles and FIP characterization vehicles. Advanced power, performance and area (PPA) analysis is conducted across domains to guide silicon and packaging technology definition to maximize technology PPA entitlement and minimize process risks and cost.

Job Role & Responsibility Description
As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs. You will directly interface with key Intel foundry customers to understand technology and library gaps and drive co-optimization with Intel foundry technology development teams and EDA partners. Your responsibility includes optimizing library circuits in close collaboration with physical design engineers to provide optimally tuned layout to improve cell performance, power and area, collaborating with EDA partners to optimize cell content in standard cell library to improve Intel technology entitlement at product level.

Required Skills and Experience

• Strong technical understanding of advanced semiconductor technology
• Strong technical understanding of foundation IP design and design-technology co-optimization
• Experience in standard cell library design with good understanding of MOSFET electrical characteristics, local layout effects, variability at advanced nodes
• Experience with library cell characterization methodology and tools and Spice circuit simulations
• Experience in semiconductor foundry ecosystem from foundry, EDA/IP, or foundry customer perspective
• Excellent oral and written communication skills
• Collaborative mindset and great team player
• Good track record of technical leadership and delivery

Preferred Skills and Experience

• Experience in product designs with good understanding of signoff methodology, tradeoffs across power, performance and tradeoff
• Familiar with pre and post Si foundry benchmarking practices
• Familiar with EDA tool design and optimization with experience in identification, design and verification of cells targeted to improve product level PPA
• Experience in foundation IP Si validation

Qualifications:

• Ph.D. or master's degree in electrical engineering or computer science
• 10+ years of industry experience

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.