Physical Design Methodology Engineer

NVIDIA has been a pioneer in technology for over two decades. The invention of the GPU in 1999 ignited the PC gaming market, transformed modern computer graphics, and revolutionized parallel computing. Today, with the global surge in artificial intelligence research, NVIDIA GPUs provide the necessary scalable and massively parallel computation power. As a "learning machine," NVIDIA continually adapts to new, challenging opportunities that only we can tackle and that have a significant impact on the world. Our mission is to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our exceptional team and see how you can make a lasting impact on the world! What You'll Be Doing: Create and enhance cutting-edge physical design methodologies for implementing GPUs, CPUs, and SoCs, focusing on optimizing Power, Performance, and Area (PPA) as well as improving the runtime efficiency of the physical design process on advanced technology nodes. Develop workflows for advanced place and route techniques, floorplanning, and chip assembly, including power and clock distribution, power and area optimization, timing analysis, IR and EM analysis. Work together with internal and external partners to enhance tools and methodologies, ensuring the delivery of top-tier Power, Performance, and Area (PPA) solutions across all our product lines Continuously strive to improve the RTL-to-GDS flow to enhance Power, Performance, and Area (PPA), address a wide range of design issues, and implement proactive interventions What We Need to See: MS in Electrical or Computer Engineering (or equivalent experience). Minimum 5 years of experience in Physical Design Engineering. Demonstrated success in enhancing Power, Performance, and Area (PPA) for high-performance and low-power designs using advanced technology nodes. Strong understanding of physical design optimization and routing methodologies at place, CTS, route, and post-route, especially power and area-efficient setup and hold optimization. Strong background of design rules in advanced technology nodes and their impact on Design Rule Check (DRC) closure and Power, Performance, and Area (PPA) optimization." Understanding of power intent files such as UPF, and use of FSDB/SAIFs for power optimization. Understanding of hierarchical design, pinning, and budgeting flows. Experience with power distribution networks, Design for Yield and Manufacturability, EM and IR closure, and thermal management. Expertise and in-depth knowledge of industry-standard EDA tools. Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.