Physical Design Manager

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary ASIC Backend Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As the ASIC Backend Manager, you will be a foundational member of our Israel R&D center, defining and executing the transition from RTL to GDS for silicon that drives hyperscale AI infrastructure. You won't just execute tasks—you will establish cutting-edge methodologies, build a high-performing team, and ensure our connectivity solutions meet the extreme performance, power, and area targets required for next-generation data centers. If you thrive on solving complex challenges in deep-submicron processes and want to shape the future of AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

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Team Leadership & Development

• Build, mentor, and lead a high-performing Backend team in Israel

• Own the end-to-end physical design flow from Synthesis to Signoff

• Lead and guide external contractors and global partners to ensure seamless execution and delivery

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Physical Implementation & Methodology

• Establish cutting-edge RTL-to-GDS flows and physical design methodologies for advanced process nodes (5nm, 3nm, and below)

• Take full ownership of physical implementation including floorplanning, P&R, CTS, power/clock distribution, and timing/physical signoff

• Drive optimal Power Performance Area (PPA) through feasibility studies for new architectures and QoR optimization

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Cross-Functional Collaboration & Technical Excellence

• Partner closely with Architecture, Design, DFT, and Product teams to achieve PPA targets

• Address complex signal integrity, thermal, and power challenges in high-speed connectivity silicon

• Manage both complex macro-level designs, subsystem integration, and full-chip implementation

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field

• 10+ years of hands-on experience in Physical Design/Backend at semiconductor companies

• Deep expertise in RTL2GDS flows including P&R, STA, physical verification (DRC/LVS), formal verification, and low-power implementation (UPF/CPF)

• Proven experience leading teams or projects with excellent communication skills and a "can-do" approach

• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)

• Experience working on advanced process technologies (5nm, 3nm, and below)

• Full-chip design experience managing both macro-level and subsystem-level integration

Preferred Qualifications

• Master's degree in Electrical Engineering or related field

• Deep understanding of Power & Noise analysis (EM/IR)

• Experience with DFT (Design for Test) integration

• Background in high-speed interfaces or data center protocols (PCIe, CXL, Ethernet)

• Experience evaluating foundry process nodes and third-party IPs

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.