Physical Design Flow Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent's Physical Engineering group is looking for seasoned Physical Design Flow Engineers to develop implementation flows and methodologies for high-performance, low-power designs on advanced technology nodes, with focus on improving Power, Performance, and Area (PPA) in taped-out designs for its next gen products.

This role is hybrid, based out of Santa Clara, CA, Fort Collins, CO or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a BS/MS in Electrical or Computer Engineering (or equivalent experience) and 5+ years of industry experience in Physical Design and CAD methodology development.

• You have proven experience developing implementation flows and methodologies for high-performance, low-power designs on advanced technology nodes, with a track record of improving Power, Performance, and Area (PPA) in taped-out designs.

• You are hands-on with industry-standard EDA tools (e.g. Fusion Compiler) for logic synthesis, place-and-route, static timing analysis, and signoff closure.

• You understand hierarchical design flows, including floorplanning, partitioning, pin placement, and chip assembly, and have experience with physical design verification (formal equivalence, timing, noise, DRC/LVS, EM/IR).

• You are comfortable scripting in Tcl, Python, and/or Perl, and you use automation to make flows more robust and efficient.

• You are proactive, able to independently drive complex technical projects with minimal oversight, and skilled at building and executing implementation plans, monitoring key indicators, and communicating resource needs.

What We Need

• Lead and contribute to cross-functional efforts to solve complex physical design challenges across multiple IPs, projects, and technology nodes.

• Develop, enhance, and maintain RTL-to-GDS methodologies spanning floorplanning, synthesis, place-and-route, static timing analysis, signoff, and assembly.

• Optimize industry-standard EDA tools and flows to improve PPA (Power, Performance, Area) and runtime efficiency, ensuring robust, scalable implementation for current and future products.

• Design and maintain custom CAD tools and implementation methods that increase automation, improve PPA, and enhance overall engineering productivity.

• Drive innovative, ML-based solutions that proactively improve automation and explore new design optimization strategies.

• Collaborate closely with physical verification, RC extraction, timing analysis, and DFT teams to ensure seamless integration and smooth execution from implementation through signoff.

What You Will Learn

• Deep exposure to cutting-edge AI and high-performance silicon across multiple IPs and technology nodes, including how different design styles and architectures drive methodology choices.

• How to architect and scale end-to-end RTL-to-GDS flows in a fast-moving environment, balancing PPA targets, runtime, and design schedule across multiple projects.

• Best practices for integrating physical design, signoff, PV/EMIR, RC extraction, STA, and DFT into a coherent, high-yield implementation methodology.

• How to leverage data and ML-based approaches for flow optimization, including building datasets from production runs and experimenting with predictive models and heuristics for PPA and runtime.

• How to effectively influence EDA vendors, translate real design challenges into actionable feature requests, and align tool roadmaps with internal product needs.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.