PD - Principal STA Signoff (Top-Level)

Join the leading chiplet startup! As an Eliyan Synthesis and STA lead, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be responsible for putting together synthesis and STA methodologies for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.

Responsibilities::
• Own Subsystem and full-chip STA signoff across all functional and test modes with complete MMMC coverage.
• Define and drive a scalable hierarchical constraints & flat Constraint methodology, including:
• ----Push down constraints, timing budgets, interface constraints (I/O delays), generated clocks, exceptions, case analysis, and mode definitions.
• ----Merging IP constraints, validated interface assumptions, updated clock/latency intent, propagated exceptions, and closure feedback to top-level signoff.
• Lead functional ECO strategy and execution:
• ----Root-cause critical paths, select optimal fixes on clock ad data, and deliver ECO-ready recommendations to implementation teams.
• ----Champion high-throughput ECO / PnR iteration methodology to reduce closure cycle time.
• Debug and resolve complex timing/constraint issues during implementation.
• Partner closely with RTL/design/DFT/physical design teams to align constraints intent, clocking architecture, and closure plan across milestones (place/CTS/route/signoff).
• Define MMMC corner strategy by stage (synthesis, PnR, signoff) and ensure consistent signoff criteria and reporting.
• Establish and maintain STA signoff collateral: signoff checklist / signoff document per foundry/node, standardized reports, and closure metrics.
• Build automation and dashboards for STA productivity: run frameworks, regression, constraints QA, PPA trending, and signoff readiness indicators.
• Support low-power timing methodology when applicable (UPF/CPF impacts: level shifters, isolation, retention, power states).

Qualifications (Minimum Required)::
• 8–12 years of hands-on experience in STA and timing closure for complex ASIC/SoC designs (block + top level).
• Strong expertise in timing constraints SDC creation, validation, and maintenance across functional + scan/test modes.
• Proven track record as a functional ECO expert—able to drive closure with actionable, implementation-friendly ECO guidance.
• Strong understanding of deep sub-micron timing effects and signoff considerations: variation/OCV, SI/noise, crosstalk, and margining concepts.
• Proficient in Tcl and at least one scripting language for flow automation and reporting.
• Ability to work cross-functionally with RTL, DFT, PD/CTS, and signoff teams; strong written and verbal communication.

Preferred (Strong Plus)::
• Advanced-node experience with TSMC 3nm/2nm (N3/N2) and/or Samsung 3nm/2nm technologies.
• Working understanding of library characterization fundamentals and timing model interpretation/debug (timing arcs, constraints arcs, NLDM/CCS concepts, LVF/variation concepts as relevant).
• Experience building reusable signoff methodologies across multiple blocks/chips, including constraints QA gates and signoff dashboards.