Packaging Design Engineer - Advanced Wafer-Level & OSAT Processes

We are seeking a highly skilled and experienced Packaging Design Engineer to lead the development of our next-generation semiconductor packaging solutions. This role is focused on the critical interface between our ICs and the final package, with a strong emphasis on advanced interconnects and outsourced semiconductor assembly and test (OSAT) management. You will be responsible for defining, developing, and qualifying high-reliability packaging processes, including but not limited to Through-Silicon Vias (TSVs), flip-chip bonding, mounting and wire bonding.

This is a key technical position where you will serve as the primary expert for wafer-level and package-level interconnects. You will work directly with our foundry partners to develop robust TSV processes and collaborate with OSATs to create and qualify cutting-edge assembly processes. Your expertise will be vital in ensuring our products meet the highest standards of performance and reliability, from initial design through to volume manufacturing.

Key Responsibilities:
• Design & Collaboration: (1) Serve as the technical lead for all outsourced packaging activities, including the selection and qualification of OSAT partners for our specific product requirements. (2) Own the package-level design and material stack-up, making critical decisions on die attach methods, underfill, and molding compounds. (3) Provide technical guidance to internal design teams on package-level design rules and best practices to ensure optimal manufacturability and reliability.
• Wafer-Level Interconnects: (1) Work directly with foundry partners to define, develop, and qualify Through-Silicon Via (TSV) processes that meet our stringent electrical and reliability requirements. (2) Drive the DFM (Design for Manufacturability) of our electrical interconnects, ensuring the process is robust for high-volume production.
• Reliability and Qualification: (1) Define and implement robust reliability test methodologies to characterize and validate new packaging processes and designs. (2) Collaborate closely with the reliability engineering team to prove in all new package designs and processes through rigorous testing and data analysis. (3) Conduct failure analysis on packaging-related issues to identify root causes and implement corrective actions, continuously improving process robustness.

Minimum Qualifications:
• Bachelor's or Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related field.
• 5+ years of experience in semiconductor packaging engineering, with a focus on advanced interconnects.
• Direct experience developing and qualifying 2.5 or 3D technologies, as well as more mature methodologies.
• Proven experience in working with and managing OSATs, including a track record of successfully bringing new packaging processes to production.
• In-depth knowledge of TSV technology, including process development, DFM, and the associated reliability challenges.
• Strong understanding of reliability physics and failure mechanisms in semiconductor packages.
• Expertise in failure analysis techniques (e.g., cross-sectioning, SEM, X-ray) and data-driven problem-solving.

Preferred Skills:
• Direct experience with the design and reliability of MEMS encapsulation.
• Knowledge of statistical process control (SPC) and its application in a high-volume manufacturing environment.
• Experience with various packaging materials, including underfills, molding compounds, and substrates.
• Familiarity with industry standards for packaging reliability (e.g., JEDEC).
• Strong communication and technical documentation skills, with the ability to articulate complex technical concepts to a variety of audiences.

nEye is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.