Package Design Engineer
Confidential
Posted: March 2, 2026
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Quick Summary
Design and develop high-performance AI memory fabrics using proprietary MIMO-over-copper technology to unlock unprecedented efficiency for AI training and inference at scale.
Required Skills
Job Description
At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
We are actively seeking a Package Design Engineer, based in Hyderabad OR Bangalore
Responsibility and Authority
Complete all Package design activities within the given time frame as defined by the project deliverables.
Complete Package design review processes with the Assembly subcons to ensure no design rule violations.
Liaise closely with the respective IC layout Engineers during Package design phase.
Complete verification of Electrical characteristics of the package and unit design using available SW Tools.
Ensure cost effective methodologies are incorporated into Kandou’s BGA substrate and LF designs (Multi Layer / Mechanical Drill / Plating Lines etc).
Provide support, guidance and instructions to Assembly / Package related activities, questions and issues.
Present detailed weekly reports of activities and progress to the cross-functional team.
Work with multi-functional groups including product design, engineering and marketing to ensure our package design/technology requirements are fully supported by Kandou’s assembly partners.
Required Competencies – Experience
Minimum 5 years experience in IC Package Design using Cadence APD / SIP.
Hands on experience using Cadence (Virtuoso / Extract IM / Power DC ) / Ansys SW Tools (SiWave / Q3D ) or similar tools.
Experience using AutoCAD tool.
Knowledge about various Electronic IC Packaging technology is a must.
Basic understanding of Thermal and Mechanical behaviour of IC Packages.
Basic understanding of IC physical layout is beneficial.
Required Competencies – Skills
Proven top-level Package design and RLC extraction experience.
Ability to perform package parasitics extraction.
Strong task management & planning ability. Proficiency in estimating timescales for design completion.
Able to work to tight and variable time scales
Strong interpersonal and communication skills.
Good networking, negotiation and influencing skills
Adept at managing communication with assembly subcontractors.
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It!
https://www.kandou.ai/