Memory Test Engineer (Non-Volatile Memory) – Contractor

Confidential

Grenoble, Auvergne-Rhône-Alpes, France permanent

Posted: February 17, 2026

Job Description

Location: Leuven (Belgium) or Grenoble (France)
Contract type: Contractor (4–6 months, duration TBD)

About Us

Vertical Compute is an early-stage deep tech startup dedicated to pioneering next-generation memory technologies for advanced computing architectures. Our mission is to redefine the traditional trade-offs of semiconductor memory devices and enable the future of computing.

We are building a high-performing, passionate team to disrupt the memory industry together.

About the Role

We are looking for an experienced Non-Volatile Memory (NVM) Test Engineer to define and deploy the full memory test strategy for our demonstrator and product development activities.

In this role, you will be responsible for setting up robust test methodologies, driving lab and FPGA-based test environments, and acting as a key interface between design, architecture, and device teams. You will notably serve as a bridge between teams, ensuring alignment across disciplines.

This position is ideal for a hands-on expert who can quickly take ownership of test definition and execution in a fast-paced startup environment.

What You Will Do

Test Strategy & Methodology

• Define and implement the full memory test plan

• Develop comprehensive test methodologies, including:

• Write/read sequencing

• Disturb tests

• Retention and thermal stress flows

• Endurance cycling

• Margining algorithms (Vread, Vwrite, pulse widths)

• Establish test procedures in close interaction with designers and architects

Test Infrastructure & Automation

• Drive FPGA and bench-level test setups

• Develop and execute digital test sequences

• Interface with the chip using:

• SPI

• QSPI

• Custom buses

• Develop, maintain, and run automation scripts (Python or similar)

Data Analysis & Feedback

• Analyze and interpret test results, including:

• Switching statistics (currents, resistance distributions)

• BER curves

• Formulate and validate failure mechanism hypotheses

• Define margin requirements for next silicon revisions

• Correlate device-level behavior with macro-level memory performance

• Work closely with design and device teams

• Provide clear, actionable feedback to internal stakeholders

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