Lead Design Verification Engineer

Job Details: Job Description: We are seeking a highly accomplished Silicon Design Verification Architect to define, architect, and deliver end‑to‑end verification strategies for complex IPs, subsystems, and SoCs. In this role, you will lead the development of scalable, reusable verification infrastructures and methodologies, drive functional and security coverage closure, and ensure first‑pass silicon success across pre‑ and post‑silicon validation. This is a hands‑on technical leadership role requiring deep expertise in UVM‑based simulation, formal and multimodal verification, and verification infrastructure architecture, as well as close collaboration with design, architecture, software, and post‑silicon teams. Key Responsibilities Define and own the verification architecture and strategy for IPs, subsystems, and full SoCs, ensuring optimal tradeoffs between completeness, performance, reuse, and scalability. Architect, implement, and maintain advanced UVM and formal‑based verification environments, including configurable, reusable testbenches and verification components. Design and integrate block‑level testbenches into chip‑level UVM environments, executing and validating complex IP and SoC integrations. Develop comprehensive test strategies, testbench architectures, and verification plans aligned with design specifications, coverage goals, and silicon milestones. Lead random and constrained‑random test generation, functional simulation, and regression strategies to uncover design gaps and corner‑case defects. Drive coverage analysis, failure root‑cause analysis, and coverage closure, ensuring measurable verification completeness and signoff readiness. Develop and execute low‑power and security validation strategies, including definition of security coverage models and deployment of security‑focused verification infrastructure. Collaborate closely with design, architecture, analog, software, and post‑silicon teams to align verification intent across the full product lifecycle. Support post‑silicon validation and debug, leveraging pre‑silicon environments and collateral to accelerate issue isolation and resolution. Mentor and influence verification engineers across teams through best practices, design reviews, and technical leadership. Additional Skills Excellent communication, technical writing, and organizational skills, with a strong record of cross‑functional collaboration. Qualifications: Minimum Qualifications BS or MS in Electrical Engineering, Computer Science, or a related field, with 10+ years of industry experience in silicon design verification. 8+ years of experience across IP‑level, subsystem‑level, and SoC‑level verification, with demonstrated ownership of complex verification architectures. Strong expertise in simulation‑based verification methodologies, including UVM, assertion‑based verification, co‑simulation, and low‑power verification. Advanced coding skills in SystemVerilog/UVM. Preferred Qualifications Proven hands‑on experience developing highly configurable and reusable Verification IP (VIP) such as AMBA, PCIe, HBM, LPDDR, or similar complex protocols. Advanced coding skills in SystemVerilog/UVM, C/C++, Python, and scripting/build systems such as Make, CMake, or Bazel. Demonstrated history of delivering robust, scalable verification tools and infrastructure that enable high‑quality, on‑time silicon. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.