IP/SOC Verification Engineer/Lead

Job Details: Job Description: Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications: Education Requirement: Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 10+ years of industry work experience, or- Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9+ years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 8+ years of related work experience. Minimum Qualifications: 9+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth know how. Solid work experience in developing System Verilog/UVM based testbench to validate the CPU Subsystems, Ethernet Subsystems, Time Sensitive Networking, USB Subsystems, Interconnects, DMA, Clock and reset, Boot flows, Power management, Low speed peripherals. Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, and Python. Proficient in debugging CPU Subsystems, NOC, Interconnects, Ethernet Subsystems, PCIe Subsystems, Data path, Clock and resets, Power management designs. Knowledge of advanced computer architecture and micro-architecture concepts. Experience with writing directed and random test cases including develop and maintain test plans, test cases. Experience with design verification and validation methodologies and strategies. Work with vendors and IP providers to integrate their IP into testbench. Work closely with architecture, design and verification teams to ensure successful Tape out. Participate in design and verification reviews, technical discussions and provide technical guidance. Good communication skills and a team player. Able to work independently in a fast-paced team and environment. Desired Requirements: Deep knowledge of system architecture including CPU, Ethernet, Time Sensitive Networking, Data path, boot flows, fabrics, interconnects, NOC, memory sub-systems, I/O peripherals (UART/SPI), bus protocols (AXI/APB), USB, DMA, CSRs, etc. Experience with boot, reset, clock, and power management. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.