FPGA Engineering Intern
KRUSH Labs B.V.
Posted: January 29, 2026
Interested in this position?
Create a free account to apply with AI-powered matching
Quick Summary
Our FPGA Engineering Intern will work on developing a hardware-in-the-loop (HIL) framework for MATLAB models on a Zynq-based FPGA platform.
Required Skills
Job Description
Our company is developing a hardware‑in‑the‑loop (HIL) framework that connects MATLAB models to a Zynq‑based FPGA platform via Ethernet. This setup enables near real‑time testing of RF/PHY functionality and allows MATLAB algorithm developers to validate their work without waiting for full hardware integration. The goal is to build a lightweight, OS‑less (or minimal) FPGA system that can exchange packets efficiently with MATLAB and provide direct access to FPGA registers/ internal signals through Ethernet. This HIL setup will accelerate our development cycle and serve as a reusable platform for future projects.
Your Mission🚀
As a Master’s thesis student, you will:
• Develop a MATLAB ↔ FPGA Ethernet communication interface for transmitting raw samples and control messages.
• Implement bare‑metal or minimal runtime on Zynq to avoid OS overhead and ensure deterministic packet flow.
• Explore the use of a secondary SFP/Ethernet interface for debug packet capture.
• Validate RF/PHY functionality by comparing FPGA output with MATLAB models.
• Deliver a reusable HIL setup supporting future system bring-up and prototyping.
• Verify/Validate the system with CocoTB.
Requirements:
• Final-year Master of Engineering (EE/Embedded/FPGA).
• FPGA design (VHDL/Verilog) and building testbenches with cocotb.
• MATLAB scripting and modeling.
• Good understanding of digital communications.
• Basic knowledge of Ethernet networking.
Nice to have: Zynq/Vivado experience, bare‑metal programming, AXI interfaces, Digital communication basics.
Benefits:
What You Will Learn
• FPGA system design and real-time communication.
• Zynq SoC development (RTL + bare-metal software).
• MATLAB–FPGA co-simulation workflows.
• Ethernet protocols and packet interface design.
• RF/PHY-level testing and validation methodology.
Why This Project Matters
This HIL framework will remove slowdowns caused by cross‑team dependencies and long hardware bring-up cycles. MATLAB modeling takes days, while FPGA development can take weeks or months—this project enables both to progress independently and much faster.
If you're enthusiastic about FPGA, communication systems, and hands-on real hardware development, we want to hear from you!