Formal Verification Infra Development Engineer

NVIDIA is looking for outstanding candidates with knowledge of formal methods. The engineer will own the task of maintaining formal verification (FV) flow across Nvidia projects, maintaining the Nvidia assertion library as well as resolving issues related to FV with various design teams and tool related issues with vendors. He will also help drive FV for RTL units for next generation chip designs. Knowledge in Generative AI Solutions with expertise in training Large Language Models (LLMs) and implementing workflows based on Pretraining, Finetuning LLMs & Retrieval-Augmented Generation (RAG).  This will involve the candidate having excellent communication skills, deep knowledge of aspects of Formal Verification as well as strong scripting skills.

What you will be doing:

• Maintaining, improving and updating assertions library. Support for both simulation and FV. 

• Identifying key behaviors for verification of DUT and creating a verification plan.

• Developing verification environment including environment assumptions, assertions and cover properties in context of the verification plan.

• Applying various FV techniques to proof correctness of digital designs.

• Developing scripts to automate the verification process.

What we need to see:

• BS/MS/PhD in CS/CE/EE/Mathematics with minimum 3+ years of industry experience.

• Excellent command on scripting.

• Knowledge/Experience in formal verification techniques.

• Hands-on experience with HDLs such as Verilog / System Verilog.

• Preferable experience with Formal Verification Tools (eg. Jasper, IFV, SMV, SPIN)
 

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