Digital Verification Engineer CH, UK, DE, DK

Confidential

Saint-Sulpice Hybrid permanent

Posted: January 30, 2026

Required Skills

Job Description

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

We are actively seeking a resourceful Digital Verification Engineer, based in either Lausanne, Switzerland, UK (Reading/Northampton), Germany (Dortmund), or Denmark.

Key Responsibilities

Develop design verification methodologies and implement standard debug flows

Work with designers in verification and validation of circuit designs

Participate in design reviews

Prepare design verification plan based on design specifications

Plan and schedule assigned projects for timely completion

Utilize the latest techniques, tools, and technologies for design verification activities

Maintain design verification environment and track & close design bugs

Skills

Must possess great communication skills, rigorous with an analytical mind and be a strong team player

Good scripting techniques, regression setup & management

Deep understanding of simulation and verification environments

Strong knowledge on Metrics-driven verification (incl. test planning and coverage closure)

Deep knowledge of simulations tools and debugging techniques

Understanding of verification planning and test bench development using the latest methodologies

Experience with 3rd party VIP usage and test development (a big plus)

Experience with Assertion Based Verification (a big plus)

Experience

5+ years’ experience in the semiconductor industry

Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC

Skilled in trade-offs between quality and schedule

Experience in constrained random test bench development

Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous

Extensive digital verification background with some UVM experience

Education

Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !

Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/

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