DFT Design Engineer

Job Details:

Job Description:

The Role and Impact:
As a Design-for-Test (DFT) Design Engineer, you will play a critical role in Intel's ability to deliver high-quality silicon solutions by ensuring robust testing and manufacturability of our products. You will collaborate with an interdisciplinary team to define and implement innovative DFT architectures and methodologies that enhance test coverage and manufacturability while meeting Intel's goals for power, performance, area, and quality. Your contributions will directly influence Intel's ability to meet stringent customer requirements and deliver high-volume manufacturing (HVM) solutions efficiently.

Key Responsibilities:
- Develop logic design, register transfer level (RTL) coding, and simulation for DFT insertion and verification.
- Define and implement DFT architecture and microarchitecture features for blocks, subsystems, and SoCs, including SCAN, MBIST, BSCAN, and test access ports (TAP).
- Optimize logic designs to meet power, performance, area, timing, test coverage, defect per million (DPM) targets, and test time/vectormemory reduction goals.
- Collaborate with cross-functional teams to integrate DFT blocks into functional IP and SoCs.
- Develop and deliver test content for manufacturing, including high-volume manufacturing (HVM) solutions on automatic test equipment (ATE).
- Drive verification of DFT features and resolve failing RTL tests to ensure functionality and correctness.
- Partner with post-silicon and manufacturing teams to validate DFT features on silicon and support debugging requirements.
- Document learnings and recommend improvements for future designs and validations.

Qualifications:

Minimum Qualifications:
- Bachelor's degree in Electronics Engineering, Computer Engineering, Computer Science, or a related field.
- 3+ years of hands-on experience with DFT insertion and verification.
- Proficiency in DFT tools and methodologies, including SCAN, MBIST/BISR, BSCAN, and TAP.
- Strong programming skills in languages such as Verilog, C++, TCL, Perl, Python, or similar.
- Solid understanding of logic and memory design principles, VLSI design flow, and computer science fundamentals such as algorithms and data structures.
- Experience with version control, configuration management, debugging, and validation practices.

Preferred Qualifications:
- Advanced degree (Master's or Ph.D.) in Electronics Engineering, Computer Engineering, Computer Science, or a related field.
- Detailed understanding of DFT principles and test CAD algorithms.
- Hands-on experience with Tessent DFT solutions and optimizing tools, flows, and methods for DFT insertion and validation.
- Familiarity with SoC development processes (e.g., synthesis, static timing analysis, formal equivalence checking).
- Exposure to Linux OS features and scripting languages.

Join a team that drives innovation and collaborates across disciplines to ensure Intel products achieve exceptional performance, quality, and manufacturability. Apply today to contribute to a cutting-edge organization shaping the future of silicon design.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.