Design Verification Engineering Manager

Job Details:

Job Description:

Intel is seeking a highly qualified candidate to lead a chiplet verification team in a dynamic and forward-thinking organization focused on next-generation semiconductor product development. Our team focuses on being nimble, adaptable, lean and efficient to drive cutting-edge, customer impacting technology development. We embrace innovative and efficient methodologies that drive at-scale product execution. Advance your career with cutting-edge verification techniques including coverage-driven verification, formal methods, and performance analysis. Lead custom SystemVerilog/UVM development, master industry-standard EDA tools, architect verification strategies for complex ASICs, and mentor emerging talent while independently driving verification closure. Join our fast-paced semiconductor team where your technical leadership shapes next-generation chip development through comprehensive methodologies and innovative verification solutions. Transform challenging projects into career-defining achievements. If you are passionate about building products faster and more efficiently than anyone else on the planet, we want you on our team.

Key Responsibilities:
• Lead and manage a team of design verification engineers, cultivating a culture of collaboration, accountability, and innovation
• Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs. Ensure meeting the required coverage levels and confirm to microarchitecture specifications.
• Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs.
• Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs.
• Investigate and Resolve Bugs: Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
• Collaborate Across Teams: Work closely with chiplet architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies.
• Absorbs learnings: From post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
• Lead and mentor others: inspire and guide junior engineers, fostering their growth and development. Your expertise will be instrumental in cultivating a collaborative and innovative environment where every team member thrives.

Qualifications:

Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
• Bachelor's degree in electrical engineering, computer engineering, computer science, or in other relevant STEM related degree.
• 6+ years of experience in ASIC/FPGA design verification
• Strong understanding of object-oriented programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies.
• Developing UVM and/or Formal based verification architectures and methodologies.
• Experience with industry standard protocols (AMBA AXI/AXI-S/CHI and communication protocols (e.g., PCIe, Ethernet, UART, SPI, I2C/I3C))
• Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
• Familiarity with coverage-driven verification, constrained-random testing and strong debugging skills.
• Experience with scripting languages.

Preferred Qualifications:
• Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ yrs. of experience.
• Skilled in various validation concepts and debug techniques relevant to ASIC/FPGA domain.
• Collaborative, able to communicate well with counter parts and stakeholders. Strong written and verbal communication skills.
• Strong analytical ability and problem-solving skills.
• Experience in defining testbench architecture, constrained random verification methodologies.
• Experience in processor-based verification using C/C++ with UVM-based verification environments.
• Define and execute validation of IPs and/or SOC from spec to tape-in including setting verification strategy, creating test bench and components, defining test plan, writing tests, debugging, coverage and analysis.
• Low power experience (e.g., UPF).
• Experience in AMBA, CXS stream, DDR, PCIe and/or Ethernet, UCIe protocols.
• Experience in EDA tools and reusable testbench for subsystem and SoC that deploys 3rd party VIPs.
• Experience with formal verification techniques and tools is an asset.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Texas, Austin

Additional Locations:

US, California, Santa Clara, US, Oregon, Hillsboro

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $256,050.00-361,480.00 USD 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.