Design Verification Engineer Lead - Bulgaria

Confidential

Hybrid freelance

Posted: November 13, 2025

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Required Skills

C++ SystemVerilog UVM Debugging Tools Test Planning Computer Architecture SOC Silicon Design Caching Memory Subsystems

Job Description

Dear Consultant,

We are looking for an experienced Design Verification Engineer Lead with strong expertise in SystemVerilog / C++ and hands-on experience across the full silicon design lifecycle.
The role focuses on developing UVM testbenches from scratch, debugging complex SoC designs, and dri...

Source: freelancermap — View full description on freelancermap →

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