CAD Engineer - Verification

WinMaxSystemsCorporation

Mountain View, CA, United States contract

Posted: August 8, 2016

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Quick Summary

Implementing formal verification methodology using Formality and SpyGlass to improve simulation and debug methodologies, with a strong technical background in RTL design and/or RTL synthesis, and experience with Verilog/SV coding.

Required Skills

Formal Verification Linting Formalization SpyGlass RTL Design RTL Synthesis Verilog SVGs RTL domain expertise EDA Modeling TCL Perl

Job Description

Job Title: Sr. CAD Engineer - Verification

Duties: - Implement Linting methotolgy using Spyglass.

- Develop Lint rules for different phase of the design.

- Implement formal vefication methodology using Formality.

- work closely with the verification team to improve simulation and debug methodolgies

Skills:

Previous experience with Formality, VCS, Verdi and Siloti..

Previous experience with SpyGlass

Strong technical background in RTL design and/or RTL Synthesis Experience with Verilog/SV coding Being able to understand and articulate good RTL coding guidelines Integrate SpyGlass tools in design flows Deployment of SpyGlass across design team Supporting designers in their production design work Work with EDA vendors to support tool evaluations and integration into the design flow Interface between the EDA vendors and designers to assist in debugging tool issues TCL/Perl/Make experience

All your information will be kept confidential according to EEO guidelines.

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