ASIC Verification Engineer (Mixed-Signal / UVM / SystemVerilog)

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Remote

Posted: March 17, 2026

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Quick Summary

Design and implement reusable verification environments for mixed-signal ASICs using SystemVerilog and UVM.

Required Skills

SystemVerilog UVM Mixed-Signal Functional Verification Formal Verification Design Collaboration Mixed-signal ASICs Concept Support Qualification Phases First-time-right silicon quality

Job Description

Design and implement reusable verification environments for mixed-signal ASICs using SystemVerilog and UVM.

Source: freelance.de — View full description on freelance.de →

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