ASIC Verification Engineer 2

Confidential

Remote job permanent

Posted: January 30, 2026

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Quick Summary

We're looking for an ASIC Verification Engineer 2 to join our team, where you'll work on validating architectural and functional blocks using simulation, formal, and coverage methods.

Required Skills

System Verilog UVM Python Simulation Formal Verification Coverage Analysis Testbench Development Regression Debugging Analytical Problem Solving

Job Description

WE'RE HIRING!

At HTG, you’ll push boundaries with the latest tech and collaborate with a team that loves what they do. Be part of a design services company that is amongst the companies that lead the world in technology and innovation.

Your next chapter starts here.

Your responsibilities include:

• Read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.

• Thoroughly validate one or more architectural functional blocks using a combination of simulation, formal, and coverage methods.

• Develop verification, functional coverage and formal verification test plans.

• Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and/or C.

• Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function's designer.

• Provide regular status updates on verification progress on a regular basis.

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