ASIC Physical Design CAD, Timing Constraint and Analysis
NVIDIA
Posted: February 10, 2026
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Quick Summary
Join our team as a Physical Design CAD, Timing Constraint and Analysis engineer in Shanghai, China. We are looking for both junior and senior engineers to work on physical design tasks, including RTL to GSDII design, synthesis, formal check, partitioning, constraint, async check, timing analysis/fixing/signoff. You will work with expertise in all areas and contribute to the development of advanced process/technology.
Required Skills
Job Description
ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.
What You’ll Be Doing
• Develop timing analysis and timing closure methodologies, and implement flow automation for large-scale, high-speed semicustom chips based on deep submicron processes.
• Establish methodologies for timing constraints and SDC (Synopsys Design Constraints) release, including automatic constraint generation, constraint linting, and validation of timing exceptions.
• Take responsibility for EDA tool evaluation, and collaborate with EDA vendors to enhance commercial timing signoff tools and constraint lint tools.
What We Need To See
• Master’s or PhD degree in Electrical Engineering or Computer Engineering, with 2+ years of hands-on experience in physical design implementation or RTL simulation.
• Proven experience in synthesis, timing constraints definition, timing analysis, and timing closure.
• Advanced proficiency in commercial STA (Static Timing Analysis) tools, such as Synopsys PrimeTime, Cadence Tempus, Synopsys TCM, or Ausdia TimeVision.
• Solid expertise in STA principles and timing signoff processes.
• Proficiency in at least one programming/scripting language, including Perl, TCL, Python, or C++.
• Strong verbal and written communication skills, with the ability to collaborate effectively in cross-functional teams.
Ways To Stand Out From The Crowd
• Experience in flow development or automation for ASIC backend design.
• Knowledge and experience in RTL simulation and validation.