ASIC Design Engineering Intern - 2026

NVIDIA builds the world's largest chips. As the chip size grows larger and larger, power efficiency become more and more important, whether the chip is used in datacenter, in cars, in PCs, and in robots. We design a PMU IP starting from 17y ago to help making the chip always working in the best efficient way for both idle scenarios and active scenarios. The PMU IP is composed by a RISC-V core and various of custom designed control logics. The HW logic collects the status from the entire chip, processing the data, and co-work with SW running on the RISC-V core to determine the best operation point. As the PMU design becomes more and more complicated and used in more and more chips, we are hiring a ASIC Design Engineer to help building a more powerful PMU. What you'll be doing: Work with IP/system-level architect to define the micro-arch of new features. Update the existing PMU IP micro-architecture to make it more easily to be leveraged by different chip. What we need to see: Pursuing Master degree and major in Electronic science & technology or related fields. Self-driving, active thinking and problem solving. Familiar with Verilog, perl (or python) script. Familiar with C/C++. 3d+ per week working day during the entire internship. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!