ASIC Design Engineer – Emulation / Runtime Enablement

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.  

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. 

Cornelis Networks is hiring talented ASIC Design Engineers with deep experience in one or more of the key areas required to build world-class SoCs deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions.

Key Responsibilities

Develop and deploy emulation and FPGA models and runtime flows, including maintenance of tests on industry-standard emulation platforms

Support enablement and validation of advanced PCIe and Ethernet interfaces; strong familiarity with speed bridges, host software, and peripheral I/O devices (I2C, SPI, UART, SM, JTAG, GPIO).

Work closely with ASIC, firmware, and software teams to facilitate comprehensive test suite execution and triage across hardware/software boundaries.

Develop, enable, and debug FPGA-based prototyping and bring-up flows and driving execution of representative HW/SW workloads.

Debug and develop emulation/prototyping transactors (e.g., PCIe, Ethernet, common and custom peripheral I/O), including root-causing protocol/throughput issues across the DUT, BFMs, bridges, and host software; enhancing transactor functionality/performance; and creating targeted tests/instrumentation to ensure robust HW/SW co-verification on platforms.

Leverage AI-assisted development and analysis tools
to accelerate engineering workflows, including (as appropriate): build/runtime flows, log/trace triage, automated issue summarization, script generation, test creation/refinement, documentation, and knowledge capture—while maintaining rigorous validation, reproducibility, and IP/security hygiene.

Provide hands-on support to Design and DV teams, sharing knowledge of emulation runtime environments and debug methodologies to help resolve issues quickly.

Demonstrate the ability to debug both hardware and software designs down to the individual line of code when necessary.

Minimum Qualifications:

10+ years in ASIC design, verification, and emulation/prototyping including successful tape-outs of complex, high-performance SoCs.

5+ years of hands-on experience with industry leading emulation and FPGA prototyping platforms such as including Cadence Palladium/Protium or Synopsys ZeBu/EP1/HAPS.

Hands-on experience with PCIe (Gen5+) and Ethernet interfaces and protocols, transactor development and debug.

Exposure to HW/SW hybrid bring up environments, including tools such as Helium or VDK.

Strong automation skills including proficiency in scripting languages (TCL, Python, Perl, Shell) to support and enhance automation tools and frameworks.

Familiarity with version control systems (git), project management tools (Jira), and strong communication skills.

Bachelor’s or master’s degree in computer engineering, Computer Science, or Electrical Engineering.

Preferred Qualifications:

Demonstrated, responsible use of AI-assisted engineering tools
(e.g., for code/scripting acceleration, debug assistance, test generation, or documentation) with an understanding of verification rigor, data sensitivity, and IP protection.

Prototyping experience is a plus (e.g., rapid proof-of-concept development, FPGA-based prototyping, or early bring-up prototypes to validate architecture, interfaces, or software flows).

Location: This is a remote position for employees residing within the United States.

We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. 

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives. 

In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave. 

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.