Analog Layout Engineer (Lead), UK, CH
Confidential
Posted: January 30, 2026
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Quick Summary
Analog Layout Engineer (Lead) at Kandou, UK, driving innovation and pushing the limits of semiconductor chip-chip link solutions.
Required Skills
Job Description
Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy-efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today but also tomorrow. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.
We are actively seeking an Analog Layout Engineer (Lead), based in UK (Reading) or CH (Lausanne)
Responsibility
Position in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes
Layout and verification of very high-speed analog circuits
Interact closely with the design team to understand requirements and implement solutions
Support IP and chip level integration
Support and interact with customers on requirements, and IP delivery
Exposure to flip-chip package technologies
Experience
Must have experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits
Must have expertise in layout of high-speed/frequency circuits like amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, buffers, regulators, filters, data converters, etc.
Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirements
Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
User of EDA tool for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc.
Skills
Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
Manage workload and schedules and report to internal management team
Background in Semiconductor Physics
Education
Graduate in E.E.